In a high speed server consisting of multiple processors, a core electronics complex, also known as a “chipset,” provides communications between processors and various support devices (e.g., random access memory and disk drives etc.). The support devices communicate with the chipset using a plurality of fast data streams over one or more busses. Information in the data streams is contained in transactions constructed from one header packet and zero, one or more data packets.
The chipset operates to combine the fast data streams into a single fast data stream. As the chipset processes transactions of the fast data streams, it may determine that a transaction is to be broadcast to multiple destinations, and repeatedly broadcast the transaction within the single fast data stream. The repeated broadcast of the transaction must be done without corrupting or significantly delaying other transactions.
The repeated broadcast of a transaction is difficult, in part because the chipset receives transactions from two or more fast data streams simultaneously and interleaves header and data packets. Since the relative ordering of data packets within a transaction must be maintained, the repeated transaction broadcast cannot affect ordering of the interleaved transactions; the data packets of each repeated transaction broadcast must also be contiguous.
Prior art solutions typically repeat header and data packets for broadcast transactions without regard to how such action affects in-progress transactions. These solutions can compromise steady-state processing of input data streams and the relative ordering of neighboring transactions. Such solutions also utilize complicated logic and are expensive to implement.